1. Field of the Invention:
The present invention relates to a digital multiplication apparatus. More particularly, the present invention relates to a multiple multiplication apparatus having a reduced size, which is suitable for implementation in semiconductor devices.
2. Description of the Related Art
As multimedia applications continue to become more popular, various data processing techniques continue to be introduced. Thus, simple multiplication devices dealing with two inputs are required to be capable of dealing with inputs of various bit sizes and outputting many multiplication results of various bit sizes. Therefore, a multiple multiplication apparatus which performs a variety of types of multiplications is widely used.
Conventional multiple multiplication apparatuses typically select one of a number of multiplication operations according to an execution instruction and perform the selected operation. It is beneficial to use multiple multiplication apparatuses because it is possible to perform many multiplications with one apparatus without requiring many separate multiplication apparatuses implemented in the hardware.
However, conventional multiple multiplication apparatuses select one result according to the execution instruction resulting from individual hardware logics embedded therein. It is inevitable therefore, that the hardware area and power consumption increases as the number of multiplications that the apparatus handles increases because conventional multiplication apparatuses use embedded individual hardware logics.
FIG. 1 schematically illustrates the operation of a conventional multiplication module. The multiplication module 105 in FIG. 1 receives an n-bit multiplier and an m-bit multiplicand and outputs an (m+n−1)-bit result, as well as a 1-bit carry. The output carry and result can also be input to other devices.
FIG. 2 is a block diagram illustrating a conventional multiple multiplication apparatus. The multiple multiplication apparatus includes k separate multiplication modules 252, 254, 256 and 258 for performing k separate multiplications, wherein k is a positive integer. Multiplicands and multipliers are extracted in a multiplier and multiplicand extractor 210 according to the execution instruction, and are then input into a plurality of multiplication modules 252, 254, 256 and 258. One of the multiplication modules is selected by the execution instruction to provide a result for the output generator 290. That is, in the conventional multiple multiplication apparatus, only one multiplication result is selected by the output generator 290. FIG. 3 shows the operation in greater detail.
FIG. 3 illustrates a multiplication operation performed in a conventional multiple multiplication apparatus.
At a first step, the execution instruction is fetched and decoded in the multiplier and multiplicand extractor. The multiplier and multiplicand extractor decodes the execution instruction and identifies the multiplication to be performed. Then, the multiplier and multiplicand extractor extracts the multiplicand and multiplier required in a multiplication module specified by the execution instruction, and delivers the extracted multiplicand and multiplier to the multiplication module. Finally, the multiplication module performs the multiplication using the extracted multiplicand and multiplier and outputs the result.
FIG. 4 is a block diagram illustrating the operation of the conventional multiple multiplication apparatus in more detail. As shown in FIG. 4, the conventional multiple multiplication apparatus includes 4 different multiplication modules 420, 440, 460 and 480. The multiplication modules generate carries CARRY1, CARRY2, CARRY3 and CARRY4, and multiplication results SUM1, SUM2, SUM3 and SUM4, respectively, which are then each delivered to an output generator 490. The multiplier and multiplicand extractor 410 fetches and decodes an execution instruction to select a desired multiplication module to perform multiplication.
The multiplier and multiplicand extractor 410 shown in FIG. 4 generates input pairs which each have 32×16, 16×16, 8×16 and 8×8 bit numbers according to the execution instruction, respectively. Then, each multiplication module performs the multiplication assigned to it and outputs the result. An output generator selects one 48-bit result from the 4 multiplied results as the final result. Data bits of the output of the multiplication module higher than a 16th bit can be ignored since the final result is to be expressed in 48 bits, while the outputs of each of the multiplication modules are expressed in 32 bits. The final result is selected based on the execution instruction.
However, the conventional multiple multiplication apparatus includes different multiplication modules which perform different multiplications. That is, two 16×16 multiplication modules, four 8×16 multiplication modules, or four 8×8 multiplication modules are required. Therefore, the hardware area of the conventional multiplication apparatus is increased as the number of multiplications to be performed increases and results in difficulties when attempting to minimize the size of the apparatus. Furthermore, the number of logic gates required to perform the various multiplications also increases, which results in a larger power consumption.
Accordingly, a need exists for a multiple multiplication apparatus which has a reduced size and reduced power consumption.